1. Field of the Invention
The present invention relates to a semiconductor chip having a through-electrode extending thicknesswise therethrough and a production method for the semiconductor chip, and to a semiconductor device including a plurality of semiconductor chips stacked one on another and each having a through-electrode extending thicknesswise therethrough and a production method for the semiconductor device.
2. Description of Related Art
A multichip module (MCM) is conventionally known as a semiconductor device which includes a plurality of semiconductor chips. In the conventional multichip module, the plurality of semiconductor chips are arranged on an insulative wiring board horizontally parallel to the wiring board. In this case, the multichip module has a greater footprint, i.e., takes a greater area when the multichip module is mounted on a second wiring board.
In this connection, an attempt is made to reduce the footprint of a semiconductor device by stacking a plurality of semiconductor chips on a wiring board in the semiconductor device. In this semiconductor device, the semiconductor chips each include a through-electrode extending thicknesswise therethrough, and vertical electrical connection of the semiconductor chips is typically achieved via the through-electrodes of the respective semiconductor chips.
FIGS. 17(a) to 17(f) are schematic sectional views for explaining a first conventional method for producing semiconductor chips each having a through-electrode.
A hard mask 103 of silicon oxide (SiO2) is formed on one surface (hereinafter referred to as “front surface”) of a semiconductor wafer (hereinafter referred to simply as “wafer”) W provided with functional devices 101. The hard mask 103 has openings 103a which each expose a predetermined portion of the functional device 101 and a portion of the wafer W on a lateral side of the functional device 101.
Where the wafer W has a diameter of 8 inches, the wafer W has a thickness of about 725 μm. Where the wafer W has a diameter of 6 inches, the wafer W has a thickness of about 625 μm.
In turn, front side recesses 102 are each formed in the portion of the wafer W exposed in the opening 103a on the lateral side of the functional device 101 by reactive ion etching (RIE). The front side recesses 102 each have a depth of about 70 μm, for example. Then, insulation films 104 of silicon oxide each having a pattern which exposes the predetermined portion of the functional device 101 are formed on exposed interior surfaces of the openings 103a and the front side recesses 102 by a CVD (chemical vapor deposition) method.
After seed layers 105 such as of copper are formed on the insulation films 104 and on the inner peripheral surfaces of the openings 103a, a metal material 106 of copper is deposited in the openings 103a and the front side recesses 102 by a plating process employing the seed layers 105 as a seed. The metal material 106 is electrically connected to the predetermined portions of the functional devices 101.
Subsequently, the front surface of the resulting wafer W, i.e., the surface of the wafer W provided with the metal material 106, is polished (ground) by a CMP (chemical mechanical polishing) method, whereby the surface of the hard mask 103 becomes flush with the surfaces of the resulting metal material portions 106. In turn, a front side insulation film 107 having openings which each expose the surface of the metal material portion 106 above the front side recess 102 is formed on the front surface of the resulting wafer W, and bumps 108 are each formed on the exposed surface of the metal material portion 106 as shown in FIG. 17(a).
In turn, a base not shown is bonded onto the front surface of the resulting wafer W, and a surface (hereinafter referred to as “rear surface”) of the wafer W opposite from the front surface is mechanically polished, whereby the thickness of the wafer W is reduced to about 55 μm. Thus, the metal material portions 106 are exposed to the rear surface of the wafer W. A part of the metal material portion 106 in the front side recess 102 serves as a through-electrode 109. The other part of the metal material portion 106 serves as an interconnection member 110 which electrically connects the through-electrode 109 to the functional device 101 as shown in FIG. 17(b).
A polishing-damage layer having polishing marks and damaged by the polishing is present in the rear surface of the wafer W. For removal of the polishing-damage layer, the rear surface of the wafer W is dry-etched by about 5 μm. At this time, the through-electrodes 109, the seed layers 105 and the insulation films 104 are barely etched thereby to project from the rear surface of the wafer W as shown in FIG. 17(c). After this step, the resulting wafer W has a thickness of about 50 μm.
Subsequently, a rear side insulation film 111 of silicon oxide is formed over the rear surface of the wafer W (see FIG. 17(d)), and portions of the rear side insulation film 111 covering the through-electrodes 109, the seed layers 105 and the insulation films 104 are polished away, whereby the through-electrodes 109, the seed layers 105 and the insulation films 104 are exposed (see FIG. 17(e)). Then, bumps 112 are each formed on the exposed surface of the through-electrode 109 and the seed layer 105 on the rear surface of the wafer W (see FIG. 17(f)). Thereafter, the wafer W is diced to provide the semiconductor chips each having the through-electrode 109.
FIGS. 18(a) to 18(f) are schematic sectional views for explaining a second conventional method for producing semiconductor chips each having a through-electrode. This production method is disclosed in International Publication Pamphlet WO98/19337. In FIGS. 18(a) to 18(f), components corresponding to those shown in FIGS. 17(a) to 17(f) are denoted by the same reference characters as in FIGS. 17(a) to 17(f), and no explanation will be given thereto.
First, the step of forming the bumps 108 on the front surface of the wafer W and the steps precedent thereto are performed in the same manner as in the first conventional production method (see FIG. 18(a)). The front side recesses 102 each have a depth of about 70 μm as in the first conventional production method. In turn, the rear surface of the wafer W is mechanically polished, whereby the thickness of the wafer W is reduced to about 80 μm. Therefore, the front side recesses 102 do not penetrate through the wafer W at this stage, so that about 10-μm thick wafer portions are present between the metal material portions 106 in the front side recesses 102 and the rear surface of the wafer W as shown in FIG. 18(b).
Then, the rear surface of the wafer W is dry-etched by about 30 μm. This step is performed in such a manner that the insulation films 104 are etched at a lower etching rate than the wafer W. Thus, the polishing-damage layer is removed, and the metal material portions 106 each covered with the seed layer 105 and the insulation film 104 project by about 20 μm from the rear surface of the wafer W as shown in FIG. 18(c).
In turn, an insulation film 115 of silicon oxide is formed over the rear surface of the wafer W (see FIG. 18(d)), and the insulation films 115, 104 and the seed layers 105 are partly removed from the rear surface of the wafer W, whereby the metal material portions 106 are exposed to the rear surface of the wafer W. Thus, a part of the metal material portion 106 in the front side recess 102 serves as a through-electrode 117, and the other part of the metal material portion 106 serves as an interconnection member 118 which electrically connects the through-electrode 117 to the functional device 101 as shown in FIG. 18(e).
Subsequently, bumps 116 are each formed on the exposed surface of the through-electrode 117 and the seed layer 105 on the rear surface of the wafer W. Thereafter, the wafer W is diced to provide the semiconductor chips each having the through-electrode 117.
The semiconductor chips produced by either of the aforesaid production methods are vertically stacked with the bump 108 of one of each adjacent pair of the semiconductor chips being connected to the bump 112 or 116 of the other semiconductor chip, whereby the semiconductor chips are electrically connected to one another. Thus, the interconnection length can be reduced. The semiconductor device has a reduced footprint on a wiring board or the like.
In the first conventional production method, the through-electrodes 109 (metal material portions 106) are partly polished together with the wafer W when the rear surface of the wafer W is polished (see FIG. 17(b)). This results in contamination of the wafer W with copper of the metal material 106,  thereby deteriorating the characteristics of the semiconductor chips. The copper is diffused to a great depth of the wafer W, and remains in the wafer W even after the removal of the polishing-damage layer (FIG. 17(c)).
The through-holes (front side recesses 102) are required to have a size (width) of about 10 μm, for example, due to tighter process rules. In this case, however, the depth of the front side recesses 102 cannot be increased to about 70 μm or greater. Therefore, the thickness of the wafer W should be reduced to 70 μm or smaller (to about 50 μm in the aforesaid example) in order to assuredly expose the metal material portions 106 (through-electrodes 109) to the rear surface. Therefore, the resulting semiconductor chips (semiconductor substrates provided by dicing the wafer W) each have a thickness of 70 μm or smaller (about 50 μm in the aforesaid example).
However, where the thickness of the semiconductor chips is reduced to 100 μm or smaller, the rigidity of the semiconductor chips is drastically reduced. When the semiconductor chips each having a smaller thickness are stacked to be assembled into a semiconductor device, the semiconductor chips are liable to warp, so that the semiconductor chips cannot properly be connected to each other or to the wiring board.
In the second production method, the metal material portions 106 (through-electrodes 117) are not exposed when the rear surface of the wafer W is polished for the thickness reduction of the wafer W. Therefore, the wafer W is free from contamination with copper. However, the semiconductor chips produced by the second method each have a reduced rigidity like those produced by the first method, because the thickness of the wafer W is finally reduced to 70 μm or smaller (to about 50 μm in the aforesaid example). Therefore, inconvenience occurs in assembling the semiconductor chips into a semiconductor device.